This application relies for priority upon Korean Patent Application No. 2000-57070, filed on Sep. 28, 2000, the contents of which are herein incorporated by reference in their entirety.
The present invention generally relates to a circuit of a semiconductor device and a structure thereof. More specifically, the present invention is directed to a transfer circuit for transferring an electrical signal without voltage drop and a structure thereof.
In order to transfer a data signal, semiconductor devices use an interconnection that is formed of a conductive layer. For example, data stored in a cell of a semiconductor memory device is read out by a sense amplifier, and an output signal of the sense amplifier is transferred to an input/output circuit through a data signal line such as a long bus line. In this case, a transfer circuit is widely used to control a signal that is transferred through the bus line. The transfer circuit has a pass transistor for transferring a signal applied to the bus line to the input/output circuit only for a required time. In other words, the output signal of the sense amplifier is transferred to the input/output circuit through a channel area of the pass transistor only while the pass transistor is turned on. An output signal of the transfer circuit is lower in voltage than that of the sense amplifier due to the pass transistor. Therefore, the input/output circuit can mistakenly operate by misrepresenting the data in the memory device.
To overcome such a problem of the transfer circuit, a transfer circuit having a boosting circuit has widely been applied to semiconductor devices.
FIG. 1 is a diagram of a conventional transfer circuit having a boosting circuit. The transfer circuit is composed of a pass transistor TP, a control transistor TCR connected to a gate electrode of the pass transistor TP, and a capacitive transistor TCAP connected to the gate electrode of the pass transistor TP. Source and drain of the pass transistor TP correspond to input and output terminals of the transfer circuit, respectively. The gate electrode of the pass transistor TP is connected to a drain of the control transistor TCR and to a gate electrode of the capacitive transistor TCAP. A source of the capacitive transistor TCAP is connected to a drain thereof. Thus, the capacitive transistor TCAP acts as a capacitor. In this case, the gate electrode of the pass transistor TP defines a boosting node BN.
An input signal Øi corresponding to a power supply voltage (VCC) is applied to the source of the pass transistor TP. First and second control signals ØCR1 and ØCR2 corresponding to a power supply voltage (VCC) are applied to source and gate electrode of the control transistor TCR, respectively. Thus, a voltage lower than the supply voltage VCC (i.e., a voltage corresponding to xe2x80x9cVCCxe2x88x92Vtxe2x80x9d) is induced to the boosting node BN. The xe2x80x9cVtxe2x80x9d denotes a threshold voltage of the control transistor TCR. If a third control signal ØCR3 corresponding to VCC is then applied to source/drain of the capacitive transistor TCAP, a voltage VBN of the boosting node BN is boosted to be much higher than VCC. Accordingly, the control transistor TCR is turned off to completely float the boosting node BN. A voltage much higher than a source voltage of the pass transistor TP is applied to the gate electrode thereof, inducing the same voltage as VCC to the drain thereof. That is, an input signal of the transfer circuit is transferred to an output terminal thereof without voltage loss.
According to such a prior art, a transmission efficiency of a signal can be maximized using a capacitive transistor TCAP. Nonetheless, since a conventional transfer circuit is composed of three transistors, there is required a transfer circuit that is compact and is suitable for more highly-integrated semiconductor devices.
Therefore, an object of the invention is to provide a compact transfer circuit that is able to maximize a transmission efficiency and is suitable for highly-integrated semiconductor devices.
Another object of the invention is to provide a structure of a compact transfer circuit that is able to maximize a transmission efficiency and is suitable for highly-integrated semiconductor devices.
According to one aspect of the present invention, the invention includes a stack gate transistor that is connected to a data signal line and a control transistor that is connected to the stack gate transistor.
The stack gate transistor has a source that is connected to the data signal line, first and second gate electrodes that are sequentially stacked, and a drain for outputting an input signal that is applied to the source. The first gate electrode is connected to a drain of the control transistor. The source of the stack gate transistor corresponds to an input terminal of a transfer circuit to which a data signal is applied, and the drain thereof corresponds to an output terminal of the transfer circuit. Source and gate electrodes of the control transistor correspond to a first control terminal to which a first control signal is applied and a second control terminal to which a second control signal is applied, respectively. The second gate electrode corresponds to a third control terminal to which a third control signal is applied.
According to another aspect of the present invention, the invention includes a control transistor and a stack gate transistor that are formed on a semiconductor substrate. The control transistor is formed at a first active region that is defined on a predetermined area of the semiconductor substrate. The stack gate transistor is formed at a second active region that is adjacent to the first active region. The stack gate transistor has a first gate electrode crossing over the second active region, a second gate electrode being stacked on the first gate electrode, and source/drain regions formed at active regions which are located at either side of the first gate electrode. The control transistor has a gate electrode crossing over the first active region and source/drain regions being formed at active regions which are located at either side of the gate electrode. A drain region of the control transistor is electrically connected to the first gate electrode of the stack gate transistor through a local interconnection.
The first gate electrode includes an extension part that is not overlapped with the second gate electrode. Thus, one end of the local interconnection is connected to the extension part of the first gate electrode and the other end thereof is connected to the drain region of the control transistor. A first gate dielectric layer intervenes between the second active region and the first gate electrode, and a second gate dielectric layer (i.e., inter-gate dielectric layer) intervenes between the first gate electrode and the second gate electrode.